Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

摘要

This document is the Accepted Manuscript version of the following article: Martin Omana, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandrasekharan Chandra Tirumurti, and Rajesh Galivanche, ???Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST???,??IEEE Transactions on Very Large Scale Integration (VLSI) System,??Vol 25 (1): 238-246, January 2017, DOI: https://doi.org/10.1109/TVLSI.2016.2572606. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.